1. Field of the Invention
The present invention relates to an antifuse element and a semiconductor device having antifuse elements. Such a semiconductor device is applicable to a field programmable gate array (hereinafter referred to as FPGA), a programmable read only memory (hereinafter referred to as PROM), or the like.
2. Description of the Related Art
A semiconductor integrated circuit device, incorporating a FPGA and PROM as gate arrays capable of being programmed in place by a user, is provided with antifuse elements. An antifuse element is composed, as mentioned in the following references, of a bottom electrode, an antifuse material layer, and a top electrode (IEEE, Electron Device Letter, Vol. 12, No. 4, April 1991 pp. 151-153, IEEE, Electron Device Letter, Vol. 13, No. 9, September 1992 pp. 488-490).
The antifuse material layer is previously formed between the bottom electrode and the top electrode of the antifuse element, and is capable of being broken down to provide an electrical connection. When it is broken down, there is formed a filament for electrically connecting the bottom electrode to the top electrode. A relatively high breakdown voltage is applied between a bottom electrode and a top electrode of the selected antifuse element.
The FPGA can be desirably programmed since the conduction or non-conduction between the bottom electrode and the top electrode is free after completion of the wiring process. Meanwhile, in the PROM, a data writing operation can be freely perfomed after completion of the wiring process.
In such an antifuse element, the following points have not been considered.
Firstly, in an antifuse element the antifuse material layer is formed on the surface of the bottom electrode in a through hole. The bottom electrode is formed in the same manufacturing process for metal interconnects. In the case of using a metallic film such as a barrier metal for the metal interconnect, there will arise unevenness or protrusions which may be sharp on the surface of the bottom electrode due to the crystal grains of the barrier metal. In view of this, at the time of breaking down the antifuse material layer, a relatively low electric field is locally applied to the antifuse material layer being formed at the plane or smooth portion of the surface of the bottom electrode, while a relatively high electric field is locally applied to the antifuse material layer being formed at portions with sharp protrusions. In other words, the breakdown state of the antifuse material layer varies in each antifuse element or depending on the location of the same in an antifuse opening. As a result, there will arise variations in ON resistance when an operational voltage is applied to the connecting portion between the bottom electrode and the top electrode. Such a variation in ON resistance will lead to a variation of the delay time of metal interconnects. As a result, the thus completed FPGA and PROM have a varying program reading speed and data reading speed respectively, so as to significantly reduce the reliability in the semiconductor device incorporating such antifuse elements.
Secondly, in the antifuse element, the bottom electrode must be electrically connected to the top electrode at the breakdown portion of the antifuse material layer, while the same must be reliably insulated at the unbroken portion thereof. For satisfactorily meeting this requirement, however, the antifuse material layer must be formed in large thickness taking account of the margin to be lost due to the sharp protrusions on the surface of the bottom electrode. Consequently, a higher breakdown voltage will be required to break down such a thick antifuse material layer. Meanwhile, however, there has been a tendency to lower the operational voltage of the semiconductor device in accordance with the higher integration of the circuits. Therefore, a sufficiently high breakdown voltage cannot be supplied unless any special means such as a voltage step-up circuit is provided. In other words, the aforementioned antifuse structure cannot cope with the tendency to lower the operational voltage of the semiconductor device.
Thirdly, in the antifuse element, the connecting cross-sectional area is small because there is only a local connection between the bottom electrode and the top electrode. Further, the metallic composition ratio of the filament will vary due to the breakdown of the antifuse material layer to form the filament. Accordingly, the application of the operational voltage will relatively increase the ON resistance so as to cause the delay time in the metal interconnect, making it impossible to increase the operational speed of the semiconductor device.
Fourthly, in the antifuse element, the heat reaction caused by Joule heat generated at the time of the breakdown of the antifuse material film will produce compounds, which constitute the filament. When both the bottom electrode and the top electrode contain mainly Al, the compounds forming the filament will also contain Al as the main component, leading to the decrease of EM (Electro-Migration) resistance in the filament. Accordingly, a long-time application of the operational voltage to the filament will enhance the probability of disconnection of the filament due to the EM, reducing the realiability for long-time operation of the semiconductor device.